Enhancing Performance and Stability of Tin Halide Perovskite Light Emitting Diodes via Coordination Engineering of Lewis Acid–Base Adducts

For resolving toxicity issues of Pb-based perovskites, Sn-based perovskites have been widely studied as a promising alternative due to similar valence electron configuration between Sn²⁺ and Pb²⁺. However, desired Sn²⁺ in the precursor solution and film is easily oxidized to Sn⁴⁺, causing detrimental Sn vacancies and impurities in the films. Unfortunately, dimethyl sulfoxide, a ubiquitously used Lewis base for the fabrication of high-quality perovskite thin films via the adduct approach, further accelerates the oxidation of Sn²⁺ in the precursor solution. Herein, N,N′-dimethylpropyleneurea (DMPU) is proposed as an alternative Lewis base for the fabrication of high-quality Sn-based perovskite thin films. The strongly coordinating Lewis base DMPU is shown to suppress the oxidation of Sn²⁺ in the precursor solution while promoting growth of uniform and highly crystalline thin films. The PEA₂SnI₄ perovskite light emitting diode (PeLED) based on DMPU demonstrates dramatically improves luminance (L): a more than sixfold enhanced external quantum efficiency (EQE) and better operational stability than those of the device fabricated without DMPU. The optimum PeLED based on DMPU achieves a maximum L and EQE of 68.84 cd m⁻² and 0.361%, respectively. This study provides an important methodological base for studying Sn perovskites for development of high-performance and eco-friendly PeLEDs.     

A Subthreshold CMOS RF Front‐End Design for Low‐Power Band‐III T‐DMB/DAB Receivers

This letter presents a CMOS RF front‐end operating in a subthreshold region for low‐power Band‐III mobile TV applications. The performance and feasibility of the RF front‐end are verified by integrating with a low‐IF RF tuner fabricated in a 0.13‐μm CMOS technology. The RF front‐end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front‐end is 13.8 mW from a 1.2 V supply.     

Utilization of the Bayesian Method to Improve Hydrological Drought Prediction Accuracy

This study established a hydrological drought forecasting system based on the Bayesian method and evaluated its utilization for South Korea. The regression result between Historical Runoff (HR) and Ensemble Streamflow Prediction Runoff (ESP_R) was used as prior information in the Bayesian method. Additionally Global seasonal forecast System 5 Runoff (GS5_R) produced using a dynamic prediction method was used in a likelihood function. Bayesian Runoff (BAY_R), as posterior information, was generated and compared with the ESP_R and GS5_R results for predictive ability evaluation. The Standardized Runoff Index (SRI) was selected for the drought prediction, and the BAY_SRI, GS5_SRI and ESP_SRI were computed using BAY_R, GS5_R and ESP_R, respectively. The Correlation Coefficient (CC), Nash-Sutcliffe Efficiency (NSE) and Receiver Operating Characteristic (ROC) score of BAY_SRI were the highest, and the Root Mean Square Error (RMSE) of BAY_SRI was the lowest among the methods. The Bayesian method improved the behavioral and quantitative error of drought prediction and the predictive ability of the occurrence of drought. In particular, the simulation accuracy was significantly improved during the flood season. Additionally, BAY_SRI represented past drought scenarios better than did the other two methods. Overall, we found that the Bayesian method could be applied for hydrological drought predictions for based on 1- and 2-month lead times.     

Micro/nanomechanical properties of aluminum-doped zinc oxide films prepared by radio frequency magnetron sputtering

Aluminum-doped zinc oxide (ZnO) was grown on glass substrates by using RF magnetron sputtering. In order to investigate the effect of growth temperature on the mechanical properties of Al-doped ZnO films, the temperature of the substrates during deposition was controlled at room temperature (R.T.), 150 °C, and 300 °C. The crystal structure and topography of the deposited films were investigated by X-ray diffraction (XRD) and Atomic Force Microscopy (AFM). The mechanical properties of films were measured by using nanoindentation and micro-reciprocating pin-on-plate tester to characterize the hardness, modulus, and tribological behavior. The tribological behavior of silicon (100) wafer was also obtained to compare with that of the Al-doped ZnO. It was found that Al-doped ZnO films with (002) oriented plane was favored at high growth temperature. The mechanical properties of the films were significantly affected by growth temperature. The film grown at room temperature showed a relatively low friction coefficient of 0.25 and high wear resistance.     

Hardware‐Software Implementation of MPEG‐4 Video Codec

This paper presents an MPEG‐4 video codec, called MoVa, for video coding applications that adopts 3G‐324M. We designed MoVa to be optimal by embedding a cost‐effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG‐4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.     

Efficient bilayer heterojunction polymer solar cells with bumpy donor–acceptor interface formed by facile polymer blend

We demonstrated a facile method for the fabrication of bilayer polymer solar cells with a controlled heterojunction structure via simple polymer blends. The spontaneous phase separation of poly(3-hexylthiophene)/polyethylene glycol blends provides a bumpy electron-donor layer with characteristic circular depressions. The diameter and depth of the circular depressions can be controlled by varying the PEG content of the blend. The deposition of -phenyl-C61-butyric acid methyl ester as an electron-acceptor layer then creates an interpenetrating donor–acceptor interface for bilayer heterojunction polymer solar cells. The bumpy morphology of the interface results in a significant enhancement in the power conversion efficiency over that of the bilayer polymer solar cells with a typical planar interface, which is mainly due to an increase of photocurrent. An estimation of the field-dependent possibility of charge separation indicates that charge extraction is more efficient than charge recombination in the bilayer devices and the increase in the interfacial area of solar cells with a bumpy-interface leads to generate more electron-hole pairs at the interface.     

Cross direction register modeling and control in a multi-layer gravure printing

For the adaptation of the roll-to-roll printing method to printed electronics, it is mandatory to increase the resolution of the register control. Therefore, it is desired to derive a mathematical model for the register and to develop a controller to reduce register error. The mathematical model of cross direction register was derived considering both a lateral motion of a moving web and a transverse position of a printing roll. The proposed mathematical model could be used to improve the performance of the cross direction (CD) register controller in a large area, roll-to-roll printing machine. The mathematical model was validated by numerical simulations and experimental verifications in various operating conditions using a multi-layer direct gravure printing machine. The results showed that the proposed model was effective in predicting the CD register in multi-layer printing.     

Digital Audio Effect System‐on‐a‐Chip Based on Embedded DSP Core

This paper describes the implementation of a digital audio effect system‐on‐a‐chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co‐design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 μm CMOS process and evaluated successfully on a real‐time test board.     

A New Field Programmable Gate Array: Architecture and Implementation

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below 20 Ω. The chip has been fabricated using a 0.8-μm n-well complementary metal oxide semiconductor technology with two layers of metalization.